1. Field of the Invention
This invention relates generally to DC to DC voltage conversion, and more specifically to increasing the efficiency of such conversion by optimizing the MOSFET gate drive signal of a switching DC to DC converter as a function of output voltage load current.
2. Description of the Related Art
Conversion of direct current (DC) voltage from one voltage level to another is a common requirement in many electronic systems. One type of voltage converter is referred to as dissipative, wherein a voltage Vin higher than the desired output voltage Vout is applied to a first input terminal of a pass transistor, while a second output terminal of the pass transistor is connected to the load to be driven at voltage Vout. The output voltage applied to the load is sampled, scaled, and compared to a reference voltage, developing an error signal which then drives a third control terminal of the transistor in such a manner as to cause the scaled output voltage to become very close to the desired reference voltage, even with variation in Vin and/or current Iout drawn by the load. The current through the pass transistor in a dissipative converter is typically constant and substantially equal to the load current. One disadvantage of the dissipative converter is that significant power, approximated by P=Iout*(Vin−Vout), is dissipated in the pass transistor, creating undesired heat and inefficiency.
A preferred type of voltage converter has become the switching converter, wherein the pass transistor is rapidly switched on and off to control the current flow to the load, hence voltage applied to the load. A switching converter having an output voltage lower than its input voltage is commonly referred to as a buck converter, while one having an output voltage higher than the input voltage is referred to as a boost converter. The ability of the switching converter to boost an input voltage to a higher level is another advantage over the dissipative converter. The efficiency of a switching converter is also typically much higher than a dissipative converter, especially in applications having a large difference between input and output voltages.
In operation, a switching converter samples and scales the output voltage and compares this scaled voltage to a reference voltage, developing an error signal. This error signal then modulates the width of a pulse-width-modulated signal which drives the control terminal of the pass transistor, for example the gate if the pass transistor is a MOSFET. The gate drive signal causes the typical enhancement-mode MOSFET to have a very low drain to source resistance during the gate drive high state, and a very high resistance during the gate drive low state. By controlling the relative on/off time of the pulse-width-modulated gate drive, the amount of average current flowing through the pass transistor to the load is adjusted to drive the output (load) voltage to the desired value. As the input voltage decreases, increasing on time of the gate drive keeps the output voltage at the desired level. Conversely, increasing input voltage causes a decrease in on time. The frequency of the gate drive signal is typically in the hundreds of kilohertz to many megahertz range.
Ideally, the pass transistor in a switching converter is either fully on, in which case its ideal resistance is zero, or fully off, in which case its ideal current flow is zero. In both ideal cases, no energy is lost in the pass transistor. Available non-ideal pass transistors, however, have non-zero on resistance Rds(on), where Rds refers to the drain to source resistance of a metal-oxide field-effect transistor (MOSFET). This non-zero Rds(on) leads to conduction loss, increasing with increasing load current. Because Rds(on) is reduced as the gate voltage is increased in an enhancement-mode MOSFET, conduction loss may be reduced by driving the gate at a higher voltage. However, the MOSFET gate capacitance must be charged or discharged at each transition. For a given gate capacitance, gate charge time increases with increasing gate voltage. As the transition times of the pass transistor become a significant fraction of the total switching signal period, the switching losses due to gate charging/discharging increase substantially.
It is desirable therefore to optimize the gate drive voltage dependent on output current, keeping the gate drive voltage as low as practical while still achieving low Rds(on). At heavy load currents, efficiency degradation is dominated by MOSFET conduction losses due to non-zero Rds(on), so it is advantageous to apply a higher gate drive voltage to decrease Rds(on). At lighter load currents, switching losses due to gate capacitance dominate, so it is advantageous to apply a lower gate drive voltage, reducing the charge and discharge times of the gate.